1. Field of the Invention
The present invention pertains to electronic system design, and more particularly to the simulation of digital circuitry.
2. Related Art
The process of designing and testing digital circuitry typically includes software simulation of the circuitry. Simulation takes place prior to development of a physical prototype, and allows economical testing of the logic of a circuit. Test vectors serve as inputs to the simulated circuitry, and the outputs are analyzed as a way of verifying the accuracy of the design.
A problem arises when a large amount of circuitry needs to be simulated. Simulation of a large circuit requires a large executable image, which can exceed the memory capacity of a simulation environment. Simulation of a system of circuits, such as a system of interoperating chips that perform in parallel, leads to the same problem. Current simulation methods deal with the image size problem by simulating a subset of the circuitry in any given test. Simulation of a system of the circuitry creates an executable image having a more manageable size. By simulating a system portion by portion, all components of the system can be tested. This creates some confidence in the accuracy of the logic of the overall system, but the value of such testing is limited. The system is never tested as a single entity, so that some doubt will remain as to the ability of the overall system to function as intended. As well as being incomplete, such testing is slow and costly. A simulation must be developed and executed for each of several subsets of the logic. Moreover, the identification of the appropriate subsets to be simulated can be difficult and time consuming.
In addition, the actual simulation of a system of components can be time consuming. Such a simulation typically proceeds sequentially, that is, step by step. At each step, a determination must be made as to which component(s) has (have) work to be done. The operation of the components must then be simulated, one component at a time. If the simulation of each component is viewed as a computational thread, then the simulation of a system of components, using current simulation methods, requires sequential execution of multiple threads. This is equivalent to the creation of a single large computational thread. While there are compilers that can parallelize simulations across multiple processors, their ability to perform load balancing and handle the different clocking requirements of multiple components is limited.
Hence, there is a need for a way to simulate a system of digital components, where the simulation is both efficient and logically comprehensive.